XYZ³nÅé«æ¥ý¾W
Xilinx Ise V6.2i ^¤å¥úºÐ¥¿¦¡ª© (¶°¦¨³nÅéÀô¹Ò¡]ISE¡^6.2iª©)(2CD)
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
³nÅé¦WºÙ:Xilinx Ise V6.2i ^¤å¥úºÐ¥¿¦¡ª© (¶°¦¨³nÅéÀô¹Ò¡]ISE¡^6.2iª©)(2CD)
»y¨tª©¥»:^¤åª©
¥úºÐ¤ù¼Æ:2¤ù¸Ë
¯}¸Ñ»¡©ú:
¨t²Î¤ä´©:WIN 9x/WIN ME/WIN NT/WIN 2000/WIN XP/WIN 2003
³nÅéÃþ«¬:¶°¦¨³nÅéÀô¹Ò¡]ISE¡^6.2iª©
µwÅé»Ý¨D:PC
§ó·s¤é´Á:2004/3/27
©x¤èºô¯¸:http://www.xilinx.com
¤¤¤åºô¯¸:http://www.xilinx.com
³nÅ鲤¶:
¾P°â»ù®æ:160
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
¯}¸Ñ»¡©ú:§Ç¸¹¾÷¦bCrack¸ê®Æ§¨¤º
³nÅ鲤¶:
Xilinx Ise V6.2i ^¤å¥úºÐ¥¿¦¡ª© (¶°¦¨³nÅéÀô¹Ò¡]ISE¡^6.2iª©)(2CD)
¤º®e»¡©ú:
¥i½sµ{ÅÞ¿è¸Ñ¨M¤è®×¨ÑÀ³°ÓÁÉÆF«ä¤½¥q¡]Xilinx ¡^ªñ¤é±À¥X¨ä¶°¦¨³nÅéÀô¹Ò¡]ISE¡^6.2iª©¡A
¬°¥i½sµ{ÅÞ¿è¦æ·~³]¥ß¤F¤S¤@Ó³nÅé©Ê¯à¨½µ{¸O¡CISE °ª³t³]p¤u¨ãªº·s¯S©Ê©M¼W±j¥\¯à¨Ï
Virtex-II ProO FPGA ¤ñ³Ì¬ÛªñÄvª§²£«~ªº©Ê¯à¥§¡§Ö 40¡A¦Ó¦¨¥»«h§C 60 ¦h¡C
ISE 6.2i ªº±À¥XÁÙ±NÁÉÆF«äªº§C¦¨¥» Spartan-3O ¨t¦Cªº©Ê¯à¤ñ«e¤@ª©¥»´£¤É°ª¹F 50¡C
·í¨Ï¥Î ISE 6.2i ¶i¦æ Virtex-II Pro FPGA ³]p®É¡A¥¦¯à±a¨Ó¤TÓ¾¹¥ó©Ò¾Ö¦³ªº³t«×Àu¶Õ¨Ã
Àu¤Æ15 ªº³]p§Q¥Î²v¡A¦P®É«O«ù 2 ¿ªº¾ãÅé¹B¦æ®É¶¡Àu¶Õ¡CÁÉÆF«ä¥Î¤á±N±q PLD ¦æ·~¤¤³Ì
§Cªº¨t²Î¦¨¥»©M³Ì°ªªº¨t²Î©Ê¯à¤¤¤j¬°¨ü¯q¡C¨Ï¥Î ISE 6.2i¡ASpartan-3 ¾¹¥óªº¥»O¯S©ÊÁÙ±N
¥]¬A§ó§Öªº¶ô RAM¦s¨ú³t«×©M¹B¦æ³t«×¶W¹L 225 MHz ªº¤º¸m¼ªk¾¹¡C¥t¥~¡A®ÉÄÁ¨ì¿é¥X
(clock-to-output) ®É¶¡¤]¤ñ«e¤@ª©¥»§Ö 35 ¨ì 40¡C³o¨Ç©Ê¯àªº´£¤Éµ²¦X·~¬É»â¥ýªº¦¨¥»
Àu¶Õ¡A±À°Ê Spartan-3 FPGA ¶i¤@¨B¶i¤J¤j§å¶qÀ³¥Î»â°ì¡A¦Ó¶Ç²Î¤W³oùجO ASIC ©M ASSP ªº»â¦a¡C
¡§Â²³æ¦a»¡¡A³o¨Ç³Ì·sªº FPGA ©Ê¯à¨½µ{¸O¡AÀ³Âk¥\©óÁÉÆF«ä¤½¥q«ùÄò±Mª`¤_³Ì¥ý¶iªºFPGA ³]p
¤u¨ã»â¾É¦a¦ìªºµ²ªG¡¨ÁÉÆF«ä¤½¥q FPGA ²£«~°õ¦æ°ÆÁ`µô Rich Sevcik »¡¡C¡§³]p¤uµ{®v»Ýn¤@
ºØ§¹¥þªº¡B±j¤jªº³nÅé®M¸Ë¡B´¹¤ù©MªA°È¸Ñ¨M¤è®×¡A¥H«K¦³®Ä¦a¸Ñ¨M¥L̪ºÃøÃD¡C§Ú̦b³nÅé©Ê¯à
¡B¥\¯à©M©ö¥Î¤è±©Ò°µªºªø´Á¤£¾Óªº´£°ª©M³Ð·s¡A¥R¤ÀÅã¥Ü¤FÁÉÆF«ä¥¿P¤O©ó´£¨Ñ§¹¥þªº¸Ñ¨M¤è®×¡C¡¨
°w¹ï°ª³t³]pªº¦Û°Ê¤Æ¤u¨ã
ISE ª©¥» 6.2i ¼W¥[¤F³\¦h°w¹ï°ª³t³]pªº·s¯S©Ê©M¼W±j¥\¯à¡AµLÁ_¦a¶°¦¨¨ì ISE ªº©ö©ó¨Ï¥Î
¡B¡§«ö¶s¡¨¦¡³]p¤èªk¤¤¡C¨Ò¦p¡A¥D°Ê®É§Ç¦¬ÀÄ (ProActive? Timing Closure) ¥]¬A¤ä
´©§ï¶iªºª«²zºî¦X§Þ³N¡A¦b¤@Ó¨BÆJ¤¤¦Û°Ê°õ¦æ²£¥Íª«²z¤W¥¿½Tªº®É¶¡ÅX°Ê¡C§G½u¾¹¤¤·sªº¦Û°Ê
«O«ù®É¶¡®ø°£¾¹©M§ï¶iªº©µ¿ð¦ôºâ¾¹µ²¦X§ó·sªº®É¶¡ÅX°Ê¬M®g¾¹¡A¯à°÷¦Û°Ê§ïµ½°ª±K«×³]pªº©Ê
¯à¡C³q¹L®ø°£¯Ó®Éªº³]p¡¥N¡A¨CÓ·s¯S©Ê³£´î¤Ö¤F¾ãÅé³]p¶g´Á®É¶¡¡C
ISE ÁÙ¯à¦Û°Ê³B²z¨ìÁÉÆF«ä FPGA ªº¥~³¡¤¶±¡C¨Ò¦p¡A¹ï¦Û°Ê§½³¡®ÉÄÁ©ñ¸m¾¹ªº¤ä´©©M¥[±j¬ù§ô¡A
¨Ï·½¦P¨B°O¾ÐÅ餶±³]pÅܱo§ó®e©ö ¡V ¹ï©ó Virtex-II Pro¡A¦³¦h¹F 96 Ó§C®ÉÄÁ·îÅܪº 200MHz
®ÉÄÁ¥i¥Î¡F¹ï©ó Spartan-3 ¾¹¥ó¡A«h¦³¦h¹F 50 Ó 166MHz °O¾ÐÅ餶±¥i¥Î¡C¦P®É¡AISE §G§½³W¹º
¾¹¡BºÞ¸}³W¹º¾¹©M®É¶¡ÅX°Ê§G§½¤Î§G½u¥\¯à¯à°÷¦Û°Ê¹ï¨ì¹F©M¨Ó¦Û Virtex-II Pro X ¾¹¥ó 10Gbps
¦ê¦C I/O ªº¸ô®|¶i¦æÀu¤Æ¡C
¡§§ÚÌ«D±`°ª¿³»PÁÉÆF«ä¦b·í«e¶}µo¤Wªº§V¤O¥H¤Î§Ú̹ï Virtex-II Pro ¾¹¥ó±j¤j©Ê¯àªº°^Äm¡A
¡¨Synplicity ¤½¥qº®u§Þ³N©x Ken McElvain »¡¡A¡§¹L¥h¤E¦~ªº¦X§@ÃÒ©ú¡A§Ú̪ºÁp¦X¶}µo¤u§@¤w
¸g¬°§Ú̪º«È¤á³Ð³y¤F¥¨¤j®Ä¯q¡C¡¨
¡§Mentor GraphicsR »P ÁÉÆF«ä¦X§@¥H«OÃÒ PrecisionR Synthesis©M ISE 6.2i ¤§¶¡¯à°÷
ºò±Kµ²¦X¡A¡¨Mentor Graphics ³]p³Ð«Ø©Mºî¦X³¡Á`¸g²z Simon Bloch »¡¡C¡§§ÚÌ»PÁÉÆF«ä¤½¥qªºªø
´Á¦X§@¤Î¹ï 6.2i ª©³nÅéÀô¹Òªº¤ä«ù¡A±N¬°§Ú̪º«È¤á±a¨Ó¥¨¤jªº©Ê¯à©M¥Í²£²vªº´£¤É¡C¡¨
Xilinx Integrated Software Environment(ISE) is known industry-wide as
the leader in programmable design. With advanced technology like
ProActive Timing Closure and Incremental Design, ISE has been
lowering design costs, and setting new benchmark standards in
performance year after year. Now the newly released ISE 6.1i further
lowers logic development and production costs through new software
features focused on delivering an average 31 faster performance than
any other PLD offering, unequaled high-speed design capabilities, and
a level of ease-of-use that solves design bottlenecks. ISE slashes
design and verification times; getting you to market first, ahead of
your competition.
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=